The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a semiconductor device and a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits.
Generally, memory cells and logic circuits are formed in a semiconductor substrate. In the case of a flash memory cell having a programmable split gates, such as a floating gate (FG), a selective gate (SG) and a control gate (CG), gate electrodes of transistors in the logic circuits are made with the programmable conducting layer of the memory cell transistors.
FIGS. 1A to 1C are cross-sectional views illustrating a method for fabricating a conventional semiconductor device having memory cells and logic circuits. In FIGS. 1A to 1C, EEPROM (Electrically Erasable Programmable Read Only Memory) cells and logic circuits are formed on the same semiconductor substrate.
Referring to FIG. 1A, after forming a field oxide layer 12 to isolate a memory cell area (X) from a logic area (Y), a first polysilicon layer 13 and a second polysilicon layer 14 are formed on the semiconductor substrate 11 and the first and second polysilicon layers 13 and 14 are patterned so as to form a floating gate (FG) and a programmable gate of a flash memory device, respectively. Subsequently, a third polysilicon layer 15 is formed on the resulting structure and patterned in order to form a selective gate (SG). At this time, the third polysilicon layer 15 remains on the logic area (Y) without the patterning process. After forming the programmable gate, a source/drain region 16 is formed in the semiconductor substrate 11. For sake of convenience, gate oxide layers, which are formed between gate electrodes and between the floating gate and the semiconductor substrate 11, are not shown in the figures.
Referring to FIG. 1B, gate electrodes 15b of transistors in the logic circuits are formed by selectively etching the third polysilicon layer 15 and source/drain regions 16a are formed.
Next, referring to FIG. 1C, a first interlayer insulation layer 17 is formed on the resulting structure including the cell and logic areas and the planarization process is applied to the first interlayer insulation layer 17. Contact holes for a metal interconnection are formed by selectively etching the first interlayer insulation layer 17 and first metal wires 18, which are in contact with the source/drain regions 16 and 16a, are formed. After forming the first metal wires 18, a second interlayer insulation layer 19 is formed on the resulting structure, a second metal wire 20 is formed on the second interlayer insulation layer 19, and a passivation layer 21 is formed on the resulting structure.
However, in the conventional memory fabricating method described above, since the memory cell and logic circuit are formed on the same semiconductor substrate, a size of the entire device is increased with the increase of the size of the memory cell area so that it is difficult to develop different appliances, such as a video controller having a high memory capacity and a micro controller unit having flash EEPROMs. Further, since the devices are implemented based on the memory fabricating method, a various techniques to implement the logic circuits are limited to the related fabricating method. Accordingly, a high-speed logic control is not optimized in the case where the memory cell and logic circuit are formed on the same semiconductor substrate.
A semiconductor device of decreases size is disclosed and which includes two stacked substrates, each of which has a memory cell area and logic circuit area. A method for fabricating the same is also disclosed.
A method for optimizing operations of memory cells and logic circuits formed on the same chip by using at least two stacked substrates, each of which has memory cells and logic circuits is also disclosed.
A semiconductor device is disclosed which comprises a first semiconductor substrate on which memory cell area is formed; and a second semiconductor substrate on which logic circuit area is formed, wherein the second semiconductor substrate is stacked on the first semiconductor substrate in order that the logic circuit area operates the memory cell area.
A method for forming a semiconductor device is disclosed which comprises the steps of: forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate.
A method for forming a semiconductor device is also disclosed which comprises the steps of: a) forming memory cells on a first semiconductor substrate, wherein the memory cells include a first metal wire; b) forming logic circuits on a second semiconductor substrate, wherein the logic circuits include a second metal wire; c) stacking the second semiconductor substrate on the first semiconductor substrate by applying a thermal treatment to the first and second metal wires in order to connect the second semiconductor substrate to the first semiconductor substrate; d) polishing a rear side of the second semiconductor substrate; e) forming an insulation layer on the rear side of the second semiconductor substrate; f) patterning the insulation layer and forming a via hole to expose the second metal wire; g) forming a metal plug in the via hole; and h) forming a conducting layer electrically connected to the second metal wire through the metal plug.